SH7619 Datasheet, PDF (48/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
Classifi-
cation Abbr.
I/O Pin Name Description
Interrupt NMI
Input Non-Maskable Non-maskable interrupt request pin. This pin must be fixed
Interrupt
high when not in use.
IRQ7 to
IRQ0
Input
Interrupt
Maskable interrupt request pins.
Request 7 to 0 _{Level-input or edge-input detection can be selected. When}
the edge-input detection is selected, the rising or falling edge
can also be selected.
Address A25 to A0 Output Address Bus These pins output addresses.
bus
Data bus D31 to D0 Input/ Data Bus
output
32-bit bidirectional bus
Bus
control
CS0, CS3, Output Chip Select 0, Chip select signals for external memory and devices.
CS4, CS5B,
3, 4, 5B, 6B
CS6B
RD
RD/WR
BS
WE3
WE2
WE1
WE0
WAIT
RAS
CAS
Output Read
Indicates that data is read from an external device.
Output Read/Write Read/write signal
Output Bus Cycle
Start
Indicates start of a bus cycle.
Output Most
Significant
Byte Write
Indicates that bits 31 to 24 of data of external memory or
devices are written to.
Output Second Byte Indicates that bits 23 to 16 of data of external memory or
Write
devices are written to.
Output Third Byte
Write
Indicates that bits 15 to 8 of data of external memory or
devices are written to.
Output Least
Significant
Byte Write
Indicates that bits 7 to 0 of data of external memory or
devices are written to.
Input Wait
Input pin used to insert wait cycles into the bus cycle when
accessing the external space
Output RAS
Connects to the RAS pin of SDRAM.
Output CAS
Connects to the CAS pin of SDRAM.
CKE
Output Clock Enable Connects to the CKE pin of SDRAM.
DQMUU
Output Most
Significant
Byte Select
Selects bits 31 to 24 of SDRAM data bus.
Rev. 5.00 Mar. 15, 2007 Page 10 of 794
REJ09B0237-0500