SH7619 Datasheet, PDF (242/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 8 Clock Pulse Generator (CPG)
PHY Clock Frequency Control Register: The PHY clock frequency control register sets the
frequency division ratio of the PHY clock.
8.2 Input/Output Pins
Table 8.1 shows the CPG pin configuration.
Table 8.1 Pin Configuration
Pin Name
Abbr. I/O
Description
Mode control pins* MD0 Input
Set the clock operating mode.
MD1 Input
Set the clock operating mode.
MD2 Input
Set the clock operating mode.
Clock input pins XTAL Output Connects a crystal resonator.
EXTAL Input
Connects a crystal resonator or an external clock.
Clock output pin CKIO Output Outputs an external clock.
Note: * The values of these mode control pins are sampled only at a power-on reset or in a
software standby with the MDCHG bit in STBCR to 1. This can prevent the erroneous
operation of this LSI.
8.3 Clock Operating Modes
Table 8.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and
the clock operating modes. Table 8.3 shows the usable frequency ranges in the clock operating
modes and the frequency range of the input clock.
Table 8.2 Mode Control Pins and Clock Operating Modes
Clock
Pin Values
Operating
Mode
MD2 MD1 MD0
Source
Clock I/O
Output
1
001
EXTAL
CKIO
2
010
Crystal resonator CKIO
5
101
EXTAL
CKIO
6
110
Crystal resonator CKIO
PLL2 PLL1
CKIO Frequency
ON (×4) ON (×1, ×2) (EXTAL) × 4
ON (×4) ON (×1, ×2) (Crystal resonator) × 4
ON (×2) ON (×1, ×2) (EXTAL) × 2
ON (×2) ON (×1, ×2) (Crystal resonator) × 2
Rev. 5.00 Mar. 15, 2007 Page 204 of 794
REJ09B0237-0500