SH7619 Datasheet, PDF (388/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Figure 13.10 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
DREQ
More than 16 or 64 Bφ
(change by the CPU, LCDC, and USBH states of using bus)
Bus cycle
CPU CPU CPU DMAC DMAC CPU
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
• Burst Mode
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed
continuously without releasing the bus mastership until the transfer end condition is satisfied.
In external request mode with level detection of the DREQ pin, however, when the DREQ pin
is not active, the bus mastership passes to the other bus master after the DMAC transfer
request that has already been accepted ends, even if the transfer end conditions have not been
satisfied.
Burst mode cannot be used when the on-chip peripheral module is the transfer request source.
Figure 13.11 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read Write Read Write Read Write
Figure 13.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
Rev. 5.00 Mar. 15, 2007 Page 350 of 794
REJ09B0237-0500