SH7619 Datasheet, PDF (407/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

14.5 Usage Notes
Section 14 Compare Match Timer (CMT)
14.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows
the timing to clear the CMCNT counter.
Peripheral operating
clock (Pφ)
Address
CMCSR write cycle
T1
T2
CMCNT
Internal write
Counter clear
CMCNT
N
H'0000
Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT
Rev. 5.00 Mar. 15, 2007 Page 369 of 794
REJ09B0237-0500