SH7619 Datasheet, PDF (535/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
SCK
(CPOL = 0)
(CPOL = 1)
Sampling
MISO/MOSI
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
SS0
Ts
Th Td
Ts: The setup time for the SCK edge. The minimum value is 0. The setting is made by the SSAST1 and
SSAST0 bits in SPICR.
Th: The hold time for the SCK edge. The minimum value is 1/2 of the period of the SCK.
Td: The idle time. A number of SCK-clock cycles from 0 to 3 is set by the FLD1 and FLD0 bits in SPICR.
Figure 16.23 SPI Data/Clock Timing 2 (CPHA = 1)
Rev. 5.00 Mar. 15, 2007 Page 497 of 794
REJ09B0237-0500