SH7619 Datasheet, PDF (554/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Initial
Bit Bit Name Value R/W Description
7
EIC6
0
R/W External Interrupt Source
6
EIC5
0
5
EIC4
0
4
EIC3
0
3
EIC2
0
2
EIC1
0
R/W These bits specify the source for interrupts generated by
R/W ^{the EIR bit. These bits can be written to from both an}
external device and the on-chip CPU. By using these bits,
R/W _{fast execution of interrupt exception handling is possible.}
R/W ^{These bits are completely under software control, and}
R/W ^{their values have no effect on the operation of this LSI.}
1
EIC0
0
R/W
0
EIR
0
R/W External Interrupt Request
While this bit is 1, the HIFINT pin is asserted to issue an
interrupt request to an external device from this LSI.
17.4.7 HIF Address Register (HIFADR)
HIFADR is a 32-bit register which indicates the address in HIFRAM to be accessed by an external
device. When using the LOCK bit setting in HIFMCR to specify consecutive access of HIFRAM,
auto-increment (+4) or auto-decrement (-4) of the address, according to the AI/AD bit setting in
HIFMCR, is performed automatically, and HIFADR is updated. HIFADR can be only read by the
on-chip CPU. Access to HIFADR by an external device should be performed with HIFADR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Initial
Bit
Bit Name Value R/W Description
31 to 10 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9 to 2 A9 to A2 All 0
R/W* HIFRAM Address Specification
These bits specify the address of HIFRAM to be
accessed by an external device, with 32-bit boundary.
1, 0
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * This bit can be only written to by an external device when the HIFRS pin is low. It
cannot be written to by the on-chip CPU.
Rev. 5.00 Mar. 15, 2007 Page 516 of 794
REJ09B0237-0500