SH7619 Datasheet, PDF (210/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when data exists in non-cacheable area and the data
bus width is larger than or equal to access size. Since the burst length is set to 1 in synchronous
DRAM burst read/single write mode, only the required data is output. Consequently, no
unnecessary bus cycles are generated even when a cache-through area is accessed.
Figure 7.16 shows the single read basic timing.
Tr
Tc1
Td1
Tde
Tap
CKIO
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D
BS
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.16 Basic Timing for Single Read (Auto Precharge)
Burst Write: A burst write occurs in the following cases in this LSI.
1. Access size in writing is larger than data bus width.
2. Write-back of the cache
3. 16-byte transfer by DMAC and E-DMAC (access to non-cacheable area)
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed consecutively four times to write 16-byte consecutive data to the SDRAM that is
connected to a 32-bit data bus. The relationship between the access size and the number of bursts
is shown in table 7.18.
Rev. 5.00 Mar. 15, 2007 Page 172 of 794
REJ09B0237-0500