SH7619 Datasheet, PDF (696/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
Default Register Bit
Values
co_st_mode[2:0]
of PHYIFCR
Mode Definitions
Register 0 Register 4
[13,12,10,8] [8,7,6,5]
000
10Base-T Half Duplex. Auto-negotiation disabled. 0000
N/A
001
10Base-T Full Duplex. Auto-negotiation disabled. 0001
N/A
010
100Base-TX Half Duplex. Auto-negotiation
1000
N/A
disabled.CRS is active during Transmit & Receive.
011
100Base-TX Full Duplex. Auto-negotiation
1001
N/A
disabled.CRS is active during Receive.
100
100Base-TX Half Duplex is advertised. Auto-
1100
0100
negotiation enabled.CRS is active during Transmit &
Receive.
101
Reserved.(Do not set this mode)
1100
0100
110
Power Down mode. In this mode the PHY wake-up N/A
N/A
in Power-Down mode.
111
All capable. Auto-negotiation enabled.
X10X
1111
22.13 Usage Notes
(1) Input clock to PHY module
The initial clock to PHY module is internal clock, mck (= ick/4), but it does work only when it is
25MHz, which is acceptable to PHY module.
It corresponds to power down mode. For example, even in the application which doesn't use the
on-chip PHY module, you have to set up the clock to the on-chip PHY so that it could be low
power consumption mode with power down mode.
(2) Treatment of Pins When PHY Power Supply is Not Used
Even when the on-chip PHY is not used, supply power to the analog power supply pins for the
PHY (Vcc1A, Vcc2A, and Vcc3A) and connect the analog ground pins for the PHY (Vss1A and
Vss2A) to the ground. Pull up the CK-PHY pin to VccQ through a resistor or pull down the
CK-PHY pin to VssQ through a register. Connect pins TxP, TxM, RxP, and RxM to the PHY
analog ground. Connect the EXERS1 pin to the PHY analog power supply without going through
a resistor. Do not connect anything to the TSTBUSA pin.
Rev. 5.00 Mar. 15, 2007 Page 658 of 794
REJ09B0237-0500