SH7619 Datasheet, PDF (534/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
TXE RXE TDMAE RDMAE SPI Transmit/Receive Operation
1
1
0
0
Full-Duplex Communication
The transmit and receive FIFOs operate at the same
time. Data in the transmit FIFO are transmitted or
received. When there is no data left in the transmit FIFO,
the transmit and receive operations end. Note that even
if only reception is to be done, dummy transmission is
necessary because only master mode is allowed in the
SPI mode.
Note: In SPI mode, settings other than the above are prohibited.
In half-duplex reception (transmission is disabled), the value output from the MOSI can be
controlled by the TXDIZ bit in SIMDR as follows.
TXDIZ = 0: Transmission is disabled, 1 is output on the MOSI.
TXDIZ = 1: Transmission is disabled, the MOSI is in the high-impedance state.
Serial Clock Timing: Timing on the data and clock lines in SPI mode is shown in figures 16.22
and 16.23. The user can select from four serial transfer formats, which differ according to the
phase and polarity of the serial clock.
SCK
(CPOL = 0)
(CPOL = 1)
Sampling
MISO/MOSI
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
SS0
Ts
Th Td
Ts: The setup time for the SCK edge. The minimum value is 1/2 of the period of the SCK. The setting is
made by the SSAST1 and SSAST0 bits in SPICR.
Th: The hold time for the SCK edge. The minimum value is 0.
Td: The idle time. A number of SCK-clock cycles from 0 to 3 is set by the FLD1 and FLD0 bits in SPICR.
Figure 16.22 SPI Data/Clock Timing 1 (CPHA = 0)
Rev. 5.00 Mar. 15, 2007 Page 496 of 794
REJ09B0237-0500