SH7619 Datasheet, PDF (31/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figure 25.31 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ....................... 748
Figure 25.32 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 749
Figure 25.33 PCMCIA Memory Card Interface Bus Timing ..................................................... 750
Figure 25.34 PCMCIA Memory Card Interface Bus Timing
(TED = 2.5 Cycles, TEH = 1.5 Cycles, One Software Wait Cycle,
One External Wait Cycle) ..................................................................................... 751
Figure 25.35 PCMCIA I/O Card Interface Bus Timing.............................................................. 752
Figure 25.36 PCMCIA I/O Card Interface Bus Timing
(TED = 2.5 Cycles, TEH = 1.5 Cycles, One Software Wait Cycle,
One External Wait Cycle) ..................................................................................... 753
Figure 25.37 DREQ Input Timing.............................................................................................. 754
Figure 25.38 TENDn, DACKn Output Timing .......................................................................... 754
Figure 25.39 SCK Input Clock Timing....................................................................................... 755
Figure 25.40 SCI Input/Output Timing in Clocked Synchronous Mode .................................... 756
Figure 25.41 SIOMCLK Input Timing....................................................................................... 757
Figure 25.42 SIOF Transmit/Receive Timing (Master Mode 1/Falling Edge Sampling).......... 757
Figure 25.43 SIOF Transmit/Receive Timing (Master Mode 1/Rising Edge Sampling)........... 758
Figure 25.44 SIOF Transmit/Receive Timing (Master Mode 2/Falling Edge Sampling).......... 758
Figure 25.45 SIOF Transmit/Receive Timing (Master Mode 2/Rising Edge Sampling)........... 759
Figure 25.46 SIOF Transmit/Receive Timing (Slave Mode 1/ Slave Mode 2) ......................... 759
Figure 25.47 I/O Port Timing ..................................................................................................... 760
Figure 25.48 HIF Access Timing ............................................................................................... 762
Figure 25.49 HIFINT and HIFDREQ Timing ............................................................................ 762
Figure 25.50 HIFRDY and HIF Pin Enable/Disable Timing...................................................... 763
Figure 25.51 MII Transmission Timing (Normal Operation)..................................................... 765
Figure 25.52 MII Transmission Timing (Collision Occurred).................................................... 765
Figure 25.53 MII Reception Timing (Normal Operation) .......................................................... 766
Figure 25.54 MII Reception Timing (Error Occurred) ............................................................... 766
Figure 25.55 MDIO Input Timing .............................................................................................. 766
Figure 25.56 MDIO Output Timing ........................................................................................... 766
Figure 25.57 WOL Output Timing ............................................................................................. 767
Figure 25.58 EXOUT Output Timing......................................................................................... 767
Figure 25.59 TCK Input Timing................................................................................................. 768
Figure 25.60 TCK Input Timing in Reset Hold State ................................................................. 768
Figure 25.61 H-UDI Data Transmission Timing ........................................................................ 768
Figure 25.62 Output Load Circuit............................................................................................... 769
Appendix
Figure C.1 Package Dimensions (BP-176) ................................................................................. 777
Rev. 5.00 Mar. 15, 2007 Page xxxi of xxxviii