GMS30C7201 Datasheet, PDF (97/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Static Memory Interface
9.4 Register Description
9.4.1 Register map
Address
BUSCbase + 00
BUSCbase + 04
BUSCbase + 08
BUSCbase + 0C
BUSCbase + 10
BUSCbase + 14
BUSCbase + 18
BUSCbase + 1C
BUSCbase + 20
BUSCbase + 24
Name
MEMCFGR0
MEMCFGR1
MEMCFGR2
MEMCFGR3
MEMCFGR4
MEMCFGR5
Testreg0 (R/W)
Testreg1 (R)
Testreg2 (R)
Testreg3 (R)
Description
Memory Configuration Register 0
Memory Configuration Register 1
Memory Configuration Register 2
Memory Configuration Register 3
Memory Configuration Register 4
Memory Configuration Register 5
0
1
3–2
31–4
Test mode bit
Test reset bit
External memory width select bit
Reserved
0
4–1
10–5
31–11
nSRAMOE
nWEN[3:0]
nCS[5:0]
Reserved
1–0
2
10–3
31–11
MemByteseq[1:0]
SRAMALatch
SRAMA
Reserved
0
4–1
8–5
9
31–10
nSRAMOutLEn
nSRAMOutEn[3:0]
nSRAMInLEn[3:0]
nSRAMInEn
Reserved
Table 9-4: Static Memory Controller register map
9.4.2
Configuration register format
Each of the 8-bit fields in the memory configuration registers defines:
• the number of wait states
• the bus width
• whether EXPCLK is enabled during accesses
• whether the bank is connected to a burst mode ROM
This is shown in Figure 9-2: Byte fields in the memory configuration register.
11
BUREN
10
76
3
Burst Read Wait State Normal Access Wait State
2
CLKEN
1
0
MemWidth
Figure 9-2: Byte fields in the memory configuration register
GMS30C7201 Data Sheet
9-7