GMS30C7201 Datasheet, PDF (320/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Debug and Test Interface
There is no parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state.
Boundary Scan (BS) Register
Purpose: The BS register consists of a serially connected set of cells around the periphery of the
device, at the interface between the core logic and the system input/output pads. This register
can be used to isolate the core logic from the pins and then apply tests to the core logic, or
conversely to isolate the pins from the core logic and then drive or monitor the system pins.
Operating modes: The BS register is selected as the register to be connected between TDI and
TDO only during the SAMPLE/PRELOAD, EXTEST and INTEST instructions. Values in the
BS register are used, but are not changed, during the CLAMP and CLAMPZ instructions. In the
normal (system) mode of operation, straight-through connections between the core logic and
pins are maintained and normal system operation is unaffected. In TEST mode (i.e. when either
EXTEST or INTEST is the currently selected instruction), values can be applied to the core
logic or output pins independently of the actual values on the input pins and core logic outputs
respectively. On the GMS30C7201 all of the boundary scan cells include an update register and
thus all of the pins can be controlled in the above manner. Additional boundary-scan cells are
interposed in the scan chain in order to control the enabling of tristateable buses. The values
stored in the BS register after power-up are not defined. Similarly, the values previously clocked
into the BS register are not guaranteed to be maintained across a Boundary Scan reset (from
forcing nTRST LOW or entering the Test Logic Reset state).
Single-step Operation
GMS30C7201 is a static design and there is no minimum clock speed. It can therefore be single-
stepped while the INTEST instruction is selected and the PLLs are bypassed. This can be
achieved by serializing a parallel stimulus and clocking the resulting serial vectors into the
boundary-scan register. When the boundary-scan register is updated, new test stimuli are
applied to the core logic inputs; the effect of these stimuli can then be observed on the core logic
outputs by capturing them in the boundary-scan register.
14-10
GMS30C7201 Data Sheet