GMS30C7201 Datasheet, PDF (295/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Register
RTCDV
Name
RTC Clock Divider
RTCCR
RTC Control
RTCTS
RTC Tic Selection
TicCLK32K
TicCLKPCLK
Type
Read/Write
Read/Write
Write-only
Write-only
Write-only
Description
Reads to the register will return only four bits of the clock
divider output. Bits [3:0] will return bits (14,11, 7, 3) of the
divider output. Write zero to bit[0] clears this divider.
This register enables the interrupt. Bit[1] enables the match
event interrupt (default disable = 0). Bit[0] enables second
event interrupt (default disable = 0).
This register is for production test purposes. Bit[0] enables
TicCLK32K for 32kHz clock replacement. Bit[1] enables
TicCLKPCLK for PCLK clock replacement.
This generates 32kHz clock for production test purposes.
This generates PCLK clock for production test purposes.
Table 13-52: RTC register description (Continued)
Register memory map
The base address of the RTC is not fixed and may be different for any particular system
implementation. The offset, however, of any particular register from the base address is
determined.
Address
RTC Base
RTC Base + 0x04
RTC Base + 0x08
RTC Base + 0x0C
RTC Base + 0x10
RTC Base + 0x14
RTC Base + 0x18
RTC Base + 0x1C
Read location
Write location
RTC data register (RTCDR)
RTC data register (RTCDR)
RTC match register (RTCMR)
RTC match register (RTCMR)
RTC status (RTCS)
Reserved
RTC clock divider (RTCDV)
RTC clock divider (RTCDV)
RTC control register (RTCCR)
RTC control register
Reserved
RTC Tic selection register (RTCTS)
Reserved
TicCLK32K
Reserved
TicCLKPCLK
Table 13-53: RTC register memory map
Note The RTC clock divider register may only be written to when in test mode.
GMS30C7201 Data Sheet
13-67