GMS30C7201 Datasheet, PDF (240/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
data. If bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1,
one and a half Stop bits are generated. If bit 2 is a logic 1 when either a 6-, 7-
or 8-bit word length is selected, two Stop bits are generated. The Receiver
checks the first Stop-bit only, regardless of the number of Stop bits selected.
This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is
generated (transmit data) or checked (receive data) between the last data word
bit and Stop bit of the serial data. (The Parity bit is used to produce an even
or odd number of 1s when the data word bits and the Parity bit are summed.)
This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic
0, an odd number of logic 1s is transmitted or checked in the data word bits
and Parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an even number
of logic 1s is transmitted or checked.
This bit is the Stick Parity bit. When bits 3, 4 and 5 are logic 1 the Parity bit
is transmitted and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic
0 then the Parity bit is transmitted and checked as a logic 1. If bit 5 is a logic
0 Stick Parity is disabled.
This bit is the Break Control bit. It causes a break condition to be transmitted
to the receiving UART. When it is set to a logic 1, the serial output (SOUT)is
forced to the Spacing (logic 0) state. The break is disabled by setting bit 6 to
a logic 0. The Break Control bit acts only on SOUT and has no effect on the
transmitter logic.
Note: This feature enables the CPU to alert a terminal in a computer
communications system. If the following sequence is followed, no erroneous
or extraneous characters will be transmitted because of the break.
This bit is the Divisor Latch Access Bit (DLAB). It must be set HIGH (logic
1) to access the Divisor Latches of the Baud Generator during a Read or Write
operation. It must be set LOW (logic 0) to access the Receiver Buffer, the
Transmitter Holding Register or the Interrupt Enable Register.
Programmable Baud Generator
The UART contains a programmable Baud Generator that is capable of taking any clock input
from DC to 8.0MHz and dividing it by any divisor from 2 to 2¹⁶–1. 4MHz is the highest input
clock frequency recommended when the divisor=1. The output frequency of the Baud
Generator is 16 x the Baud [divisor # = (frequency input) / (baud rate x 16)]. Two 8-bit latches
store the divisor in a 16-bit binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud Generator. Upon loading either of the
Divisor Latches, a 16-bit Baud counter is immediately loaded.
Table 13-8: Baud rates on page 13-13 provide decimal divisors to use with a crystal frequency
of 3.6864MHz. For baud rates of 38400 and below, the error obtained is minimal. The accuracy
of the desired baud rate is dependent on the crystal frequency chosen. Using a divisor of zero is
not recommended.
13-12
GMS30C7201 Data Sheet