GMS30C7201 Datasheet, PDF (140/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.6 LCD Timing 2 Register
LCD Timing 2 Register (LcdTiming2) contains seven different bit-fields that are used to control
various functions associated with the timing of the LCD controller.
11.6.1 Pixel Clock Source (PCS)
This bit controls the source of the pixel clock. It can either be the video bus clock, or it can be
the VGA clock. Selecting the video bus clock means that the VGA clock can be used for the
48MHz clock for FastIR when using only the LCD. Selecting the VGA clock means that the
LCD and the VGA can be operated from the same clock when sharing data.
11.6.2 Pixel Clock Divider (PCD)
The 5-bit pixel clock divider (PCD) field is used to select the frequency of the LcdCP clock
signal to the LCD panel. PCD can generate a range of LcdCP clock frequencies from LcdClk/
2 to LcdClk/33, where LcdClk is the clock selected by LCS. The frequency of the pixel clock
for a set PCD value can be calculated using the following equation:
PixelClock = ₍---P-L---C-c---dD---C---+--l--k-2---₎-
Note that in the case of the LCD, the pixel clock is not the frequency of some nominal clock
rate that individual pixels are output to the LCD. It is the frequency of the LcdCP signal. In
normal mono mode (4-bit interface), four pixels are output per LcdCP cycle, so the PixelClock
is one quarter the nominal pixel rate. In the case of 8-bit interface mono, PixelClock is one
eighth the nominal pixel rate, since 8 pixels are output per LcdCP cycle. In the case of color,
PixelClock is 0.375 times the nominal pixel rate, because 2²/₃ pixels are output per LcdCP
cycle. If the LCD and VGA are operating concurrently, and sharing DMA data, then in color
mode the pixel clock should normally be ³/₈ the VGA clock. To achieve this, PCD should be
programmed to the value 0 and the skip4 bit set to “1”. The skip4 bit produces a null clock cycle
(no high phase) every fourth clock cycle.
11.6.3 AC-bias Pin Frequency (ACB)
The 5-bit AC-bias frequency (ACB) field is used to specify the number of line clock periods to
count between each toggle of the AC-bias pin (LcdAC). The value programmed is the number
of lines between transitions, minus 1.
Note The ACB bit field had no effect on LcdAC in active mode. The pixel clock transitions
continuously in active mode and the AC Bias line is used as an output enable signal.
11.6.4 Invert VSync (IVS)
The Invert VSync (IVS) bit is used to invert the polarity of the LcdFP signal. When IVS=1,
LcdFP is active LOW. When IVS=0, LcdFP is active HIGH.
11.6.5 Invert Hsync (IHS)
The Invert HSync (IHS) bit is used to invert the polarity of the LcdLP signal. When IHS=1,
LcdLP is active LOW. When IHS=0, LcdLP is active HIGH.
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GMS30C7201 Data Sheet