GMS30C7201 Datasheet, PDF (71/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
• The PMU state machine will enter DEEP SLEEP mode (via the intermediate states
shown in Figure 7-2: Power Management State Diagram on page 7-6).
• When the RTC timer alarm is activated, the PMU automatically wakes up into SLOW
mode, but with the new FCLK frequency of 58.9824Mhz.
• The CPU may write 0x620 to the Clock Control register, which enables CCLK and
VCLK, and retains the new FCLK frequency.
SOFTWARE GENERATED WARM RESET
Figure 7-4: Software Generated Warm Reset
• The CPU writes ‘1’ to the WarmReset bit of RESET/Status register. The PMU Drives
nRESET low.The internal chip reset, BnRES is driven low.The PMU detects that the
bidirectional nRESET pin is low. nRESET is filtered by a de-bounce circuit. Note
that this means that nRESET will remain low for a minimum of 16ms. BnRES
becomes active once the de-bounced nRESET goes high once more, which disables
PLL1 and PLL2. The CPU may read the RESET register, which will return 0x106:
Bit
Meaning
bit 1 set:
PLL1 has been ‘unlocked’
bit 2 set:
PLL2 has been ‘unlocked’
bit 8 set:
A RESET event has occurred.
Table 7-14: Bit Settings for a Software Generated Warm RESET within RESET STATUS
register
GMS30C7201 Data Sheet
7-15