GMS30C7201 Datasheet, PDF (93/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Static Memory Interface
9.2 Hardware Interface and Signal Description
The Static Memory Controller module is connected to the ASB bus. Table 9-1: Static Memory
Controller ASB signal descriptions shows the internal bus interface signals to the Static
Memory Controller.
Name
BA[28:26, 5:0]
BD[10:0]
BCLK
BnRES
BWAIT
BERROR
BLAST
BSIZE[1:0]
BTRAN[1:0]
BWRITE
DSELSRAM
DSELREG
EXPRDY
nWEN[3:0]
nWEF[3:0]
nSRAMOE
nCS[5:0]
SRAMA[1:0]
nSRAMALatch
BMemByteSeq[1:0]
Type Description
In
System address bus.
InOut Bidirectional system data bus.
In
The ASB system clock
In
AMBA asynchronous reset. This signal is negative active.
Out This slave response signal is driven when the BUSC is selected,
and is used to indicate if the memory has completed its current
transfer.
Out Slave response signal.
Out Slave response signal.
In
The signals indicate the size of the transfer, which may be byte,
halfword or word.
In
These signals are used to determine access type.
In
When LOW, Read; when HIGH, Write.
In
When HIGH, this signal indicates that the Bus controller is
selected.
In
When HIGH, this signal indicates that one of the bank
configuration registers is selected.
In
Expansion channel ready. When LOW, during phase one this
signal will force the current memory transfer to be extended.
Out These signals are active LOW write enables for each of the
memory byte lanes on the external bus.
In
These optional connections use PADs feedback from the external
side of the nWEN[3:0] PADs. They are used to guarantee address
and chip select hold time when any write enable is LOW.
Out This is the active LOW output enable for devices on the external
bus.
Out Active LOW chip selects.
Out These signals form the lower bits of the external address bus. They
are used to control accesses to 16- or 8-bit memories when the bus
requests an access size larger than the memory.
Out When LOW, transparent address latch enable.
Out These signals control byte sequencing for the Data In and Data Out
paths.
Table 9-1: Static Memory Controller ASB signal descriptions
GMS30C7201 Data Sheet
9-3