GMS30C7201 Datasheet, PDF (85/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
SCLK
SCKE[3:1]
SCKE[0]
nSCS[3:1]
(high)
nSCS[0]
nSRAS
nSCAS
nSWE
SA[13:0]
SDQML,
SDQMU
SD[15:0]
Data bus driven by GMS30C7201 (D=0)
Active (open bank)
Command
Burst write
Command
Data to SDRAM
Figure 8-3: Example SDRAM burst write
Note If the D bit is cleared (in the SDRAM configuration register) the GM30C7201 drives the
data lines before and after the write burst sequence. See section 8.4.1
GMS30C7201 Data Sheet
8-13