GMS30C7201 Datasheet, PDF (145/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.9 LCD DMA Base Address Register
The LCD DMA base address register (LcdDBAR) is a read/write register used to specify the
base address of the off-chip frame buffer for the LCD. Addresses programmed in the base
address register must be aligned on sixteen-word boundaries, thus the least significant six bits
(LcdDBAR[5:0]) must always be written with zeros. Only 26 bits of the register are valid
(including the LS 6bits which must be zero), because LCD DMA is only allowed from SDRAM.
The 26 bit address range allows the LCD DMA to access any address within the SDRAM. The
upper address lines are not needed, because these are the address lines used to select which
device is accessed, but the LCD always accesses SDRAM. The user must initialize the base
address register before enabling the LCD, and may also write a new value to it while the LCD
is enabled to allow a new frame buffer to be used for the next frame. The user can change the
state of LcdDBAR while the LCD controller is active, after the Next Frame (Next) status bit is
set within the LCD’s status register that generates an interrupt request. This status bit indicates
that the value in the base address pointer has been transferred to the current address pointer
register and that it is safe to write a new base address value. This allows double-buffered video
to be implemented if required.
Bit
5-0
25-6
31-26
Name
-
LcdDBAR
-
Description
Reserved
Should always be written zero
LCD DMA Channel Base Address Pointer
16-word aligned base address in SDRAM of the frame buffer
within off-chip memory.
Reserved
Should be written zero
Table 11-9: LCD DMA Base Address Registers
11.9.1 VGA DMA Base Address Register
The VGA DMA base address register is the same as the LCD base address register, but for the
VGA display.
GMS30C7201 Data Sheet
11-17