GMS30C7201 Datasheet, PDF (84/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
A25
A24
Device selected
0
0
Device 0
0
1
Device 1
1
0
Device 2
1
1
Device 3
Table 8-9: SDRAM device selection
SCLK
SCKE[3:1]
SCKE[0]
nSCS[3:1]
(high)
nSCS[0]
nSRAS
nSCAS
nSWE
(high)
SA[13:0]
SDQML,
SDQMU
SD[15:0]
Active (open bank)
Command
Burst read
Command
Data from SDRAM _{Data bus driven by GMS30C7201 (D=0)}
Figure 8-2: Example SDRAM burst read
Note If the D bit is cleared (in the SDRAM configuration register) the GM30C7201 starts
driving the data bus immediately after the last read cycle ends. See section 8.4.1
8-12
GMS30C7201 Data Sheet