GMS30C7201 Datasheet, PDF (197/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
hardware which restricts the maximum amount of data transmitted or received. It is up to the
user to maintain these limits. If a data field which is not a multiple of 8-bits is received an abort
is signalled. Also note that each byte within the data field is transmitted and received starting
with its LSB and ending with its MSB.
CRC Field
The FIr uses the established 32-bit cyclical redundancy check (CRC-32) to detect bit errors
which occur during transmission. A 32-bit CRC is computed using the address, control, and data
fields, and is included in each frame. A separate CRC generator is implemented in both the
transmit and receive logic. The transmitter calculates a CRC while data is actively transmitted
byte shifting each byte transmitted through its serial shifter LSB first, then places the inverse of
the resultant 32-bit value at the end of each frame before the flag is transmitted. In a similar
manner, the receiver also calculates a CRC for each received data frame, and compares the
calculated CRC to the expected CRC value contained within the end of each received frame. If
the calculated value does not match the expected value, an interrupt is signalled. The CRC
computation logic is preset to all ones before reception/transmission of each frame and the result
is inverted before it used for comparison or transmission. Note that unlike the address, control,
and data fields, the 32-bit inverted CRC value is transmitted and received from least significant
byte to most significant, and within each byte the least significant nibble is encoded/decoded
first. The cyclical redundancy checker uses the 32 term polynomial:
x)= (x³² + x²⁶ + x²³ + x²² + x¹⁶ + x¹² + x¹¹ + x¹⁰ + x⁸ + x⁷ + x⁵ + x⁴ + x² +
Baud Rate Generation
The baud rate is derived by dividing down a fixed 48MHz clock generated by one of the two
on-chip PLLs by six. The 8MHz baud (time-slot) clock for the receive logic is synchronized
with the 4PPM data stream each time a transition is detected on the receive data line using a
digital PLL. To encode a 4.0Mbps data stream, the required “symbol” frequency is 2.0MHz,
with four chips per symbol at a frequency of 8.0MHz. Receive data is sampled half way through
each time-slot period by counting three out of the six 48MHz clock periods which make up each
chip. Refer to Figure 12-12: 4PPM Modulation Example on page 12-41. The symbols are
synchronized during preamble reception. Recall that the preamble consists of four symbols
repeated sixteen times. This repeating pattern is used to identify the first time-slot or beginning
of a symbol, and resets the two-bit chip counter logic, such that the 4PPM data is properly
decoded.
Receive Operation
The IrDA standard specifies that all transmission occurs at half-duplex. This restriction forces
the user to enable one direction at a given time; either the transmit or receive logic, but not both.
However, the FIr’s hardware does not impose such a restriction.The user may enable both the
transmitter and receiver at the same time. Although forbidden by the IrDA standard, this feature
is particularly useful when using the FIr’s loop back mode, which internally connects the output
of the transmit serial shifter to the input of the receive serial shifter.
After the FIr is enabled for 4.0Mbps transmission, the receiver logic begins by selecting an
arbitrary symbol boundary, receives four incoming 4PPM symbols from the input pin using a
serial shifter, and latches and decodes the symbols one at a time. If the symbols do not decode
to the correct preamble, the chip counter’s clock is forced to skip one 8MHz period, effectively
delaying the chip count by one. This process is repeated until the preamble is recognized,
signifying that the chip counter is synchronized. The preamble may be repeated as few as
sixteen times, or may be continuously repeated to indicate an idle receive line.
GMS30C7201 Data Sheet
12-43