GMS30C7201 Datasheet, PDF (248/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
UART enable register
Bit
Description
0
0 = UART disable (power-down, default value), UART Clock
stop
1 = UART enable
Table 13-12: UART enable register
UART test input register
This register is for programming on TIR[4:0] when the TIR[5] is set.
Bit
Description
6
This bit selects the source clock of the UART core block.
0 = the original UART clock(=3.6864MHz)
1 = TIC clock whenever the TIC clock port (UartTICCLK) is
accessed, the TIC clock is generated.
5
This bit selects the source of the internal NRI, SIN, NCTS,
NDSR and NDCD inputs. When it is 0, the external inputs
from PADs are used. When it is set, the values programmed on
TIR[4:0] are internally driven into the UART Core block to
corresponding lines.
4
Programmable NDCD input when the TIR[5] is set. When the
TIR[5] is 0 (default), the external input from PAD is used
(normal operation).
3
Programmable NDSR input when the TIR[5] is set. When the
TIR[5] is 0 (default), the external input from PAD is used
(normal operation).
2
Programmable SIN input when the TIR[5] is set. When the
TIR[5] is 0 (default), the external input from PAD is used
(normal operation).
1
Programmable SIN input when the TIR[5] is set. When the
TIR[5] is 0 (default), the external input from PAD is used
(normal operation).
0
Programmable NRI input when the TIR[5] is set. When the
TIR[5] is 0 (default), the external input from AFE I/F is used
(normal operation).
Table 13-13: UART test input register
13-20
GMS30C7201 Data Sheet