GMS30C7201 Datasheet, PDF (116/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PCMCIA Interface
Bit Description
4
In ATA mode, the value of this bit appears at
CA24
3
In ATA mode, the value of this bit appears at
CA23
2
In ATA mode, the value of this bit appears at
CA22
1
In ATA mode, the value of this bit appears at
CA21
0
ATA Mode bit
“0”: PCMCIA Mode (I/O Mode)
“1”: ATA Mode
Table 10-16: ATA Interface Control Register
Recommended Value for Access Timing Control Register
Memory Card Recommended Value
100 ns
0 000 00 00
150 ns
0 000 01 01
200 ns
0 001 01 01
250 ns
0 010 01 01
300 ns
0 01101 01
600 ns
Read:0 110 10 10
Write:0 110 10 10
I/O Register
x 010 10 01
Table 10-17: Access Timing Control Register Values
10.2.1 Test mode registers
The following registers are used for test purposes only. Each input test register’s output bit is
multiplexed with the corresponding input signal of AMBA or PCMCIA input signal to the
designed PCMCIA Host Bus adapter. So, in test mode, the function of designed PCMCIA HBA
can be done exactly. Output signals are also stored in the output test registers and can be read
by the host in test mode.These test registers are enabled only test mode and can be reset by the
command of Host.
By using this scheme of test methodology, the function of PCMCIA Host Bus Adapter can be
exactly examined without the help of other system peripheral blocks because all input signals
and output signals which communicate with other peripherals are derived from input test
registers and stored into output test registers. Only critical system components such as the bus
decoder and arbiter and Test mode controller which act as bus master are required for testing.
The following test register description gives only the information about the counterpart signal
of normal operation.
10-16
GMS30C7201 Data Sheet