GMS30C7201 Datasheet, PDF (86/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
SCLK
SCKE[3:0]
nSCS[0]
nSCS[1]
nSCS[2]
nSCS[3]
nSRAS
nSCAS
nSWE
SA[13:0]
SDQML,
SDQMU
SD[15:0]
Data bus driven by GMS30C7201 if SDRAM configuration register bit D=0
Precharge
(all banks)
Staggered Refresh
Figure 8-4: Example SDRAM refresh, all banks enabled
Note If the D bit is cleared (in the SDRAM configuration register) the GM30C7201 drives the
data lines to avoid floating inputs. See section 8.4.1
8-14
GMS30C7201 Data Sheet