GMS30C7201 Datasheet, PDF (79/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
D
SDRAM bus tri-state control
D = 0 the controller drives the last data onto the SDRAM data bus (default)
D = 1 the SDRAM bus is tri-stated except during writes
This bit should be cleared before the IC is programmed into a low power mode. Driving the data
lines avoids floating inputs which could increase device power consumption. During normal
operation the D bit should be set, to avoid data bus drive conflicts with SDRAM.
C
SDRAM clock enable control
C = 0 the clock enable of all IDLE devices are de-asserted to save power
(default)
C = 1 all clock enables are driven HIGH continuously
During power-up initialization, it is important that the E[3:0] and the R bits are set in the correct
sequence.
GMS30C7201 Data Sheet
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