GMS30C7201 Datasheet, PDF (243/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Note
Bit 6:
This bit is the Transmitter Empty (TEMT) indicator. Bit 6 is set to a logic 1
whenever the Transmitter Holding Register (THR) and the Transmitter Shift
Register (TSR) are both empty. It is reset to a logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode this bit is set to one
whenever the transmitter FIFO and register are both empty.
Bit 7:
In the 16450 mode this is a 0. In the FIFO mode LSR7 is set when there is at
least one parity error, framing error or break indication in the FIFO. LSR7 is
cleared when the CPU reads the LSR, if there are no subsequent errors in the
FIFO.
The Line Status Register is intended for read operations only.
FIFO Control Register
This is a write-only register at the same location as the IIR (the IIR is a read-only register). This
register is used to enable the FIFOs, clear the FIFOs and set the RCVR FIFO trigger level.
Bit 0:
Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs. Resetting
FCR0 will clear all bytes in both FIFOs. When changing from FIFO Mode to
16C450 Mode and vice versa, data is automatically cleared from the FIFOs.
This bit must be a 1 when other FCR bits are written to or they will not be
programmed.
Bit 1:
Writing a 1 to FCR1 resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
Bit 2:
Writing a 1 to FCR2 resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
Bit 3:
FCR3 is not used.
Bit 4, 5: FCR4 to FCR5 are reserved for future use.
Bit 6, 7: FCR6 and FCR7 are used to set the trigger level for the RCVR FIFO interrupt.
FCR[7:6]
RCVR FIFO
Trigger Level (Bytes)
00
01 (default)
01
04
10
08
11
14
Table 13-9: RCVR FIFO interrupt
Interrupt Identification Register
In order to provide minimum software overhead during data character transfers, the UART
prioritizes interrupts into four levels and records these in the Interrupt Identification Register.
The four levels of interrupt conditions are, in order of priority:
• Receiver Line Status
• Received Data Ready
• Transmitter Holding Register Empty
• MODEM Status.
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest
priority pending interrupt to the CPU. While this CPU access is occurring, the UART records
new interrupts, but does not change its current indication until the access is complete.
Table 13-6: Summary of registers on page 13-10 shows the contents of the IIR.
GMS30C7201 Data Sheet
13-15