GMS30C7201 Datasheet, PDF (244/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Details on each bit are outlined below.
Bit 0:
This bit can be used in a prioritized interrupt environment to indicate whether
an interrupt is pending. When bit 0 is a logic 0, an interrupt is pending and the
IIR contents may be used as a pointer to the appropriate interrupt service
routine. When bit 0 is a logic 1, no interrupt is pending.
Bit 1 and 2: These two bits of the IIR are used to identify the highest priority interrupt
pending as indicated in Table 13-10: Interrupt control functions on page 13-
16.
Bit 3:
In the 16450 mode this bit is 0. In the FIFO mode, this bit is set along with bit
2 when a time-out interrupt is pending.
Bit 4 and 5: These two bits of the IIR are always logic 0.
Bit 6 and 7: These two bits are set when FCR0 = 1.
FIFO
Mode
Only
Interrupt Identification
Register
Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Interrupt Set and Reset Functions
Priority
Level
-
Highest
Second
Second
Third
Fourth
Interrupt Type
Interrupt Source
Interrupt Reset Control
None
None
-
Receiver Line
Status
Overrun Error or Parity Error
or Framing Error or Break
Interrupt
Reading the Line Status
Register
Receiver Data
Available
Receiver Data Available or
Trigger Level Reached
Reading the Receiver
Buffer Register or the FIFO
drops below the trigger
level
Character Time-out
Indication
No Characters have been
removed from or input to the
RCVR FIFO during the last 4
Character times and there is at
least 1 Character in it during
this time
Reading the Receiver
Buffer Register
Transmitter Holding Transmitter Holding Register
Register Empty
Empty
Reading the IIR Register (if
source of interrupt) or
writing into the Transmitter
Holding Register
MODEM Status
Clear to Send or Data Set
Ready or Ring Indicator or
Data Carrier Detect
Reading the MODEM
Status Register
Table 13-10: Interrupt control functions
Interrupt Enable Register
This register enables the five types of UART interrupts. Each interrupt can individually activate
the interrupt (INTUART) output signal. It is possible to totally disable the interrupt Enable
Register (IER). Similarly, setting bits of the IER register to a logic 1, enables the selected
interrupt(s). Disabling an interrupt prevents it from being indicated as active in the IIR and from
13-16
GMS30C7201 Data Sheet