GMS30C7201 Datasheet, PDF (35/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Architecture Overview
3.3 Peripheral DMA
3.3.1 Overview
GMS30C7201 incorporates a three-channel, general-purpose DMA controller which operates
on the ASB. The DMA controller is an AMBA compliant ASB bus master with a higher
arbitration priority than either the ARM or Piccolo DSP coprocessor, to ensure low DMA
latency. Since, however, the main ASB bus always has lower priority access to the SDRAM
controller than the video bus, it will always get lower priority access to SDRAM than the LCD
and VGA.
3.3.2 Transfer sizes
The devices that make use of the peripheral DMA are:
1 USB
2 Fast/Medium IR
3 Sound output
The USB and FIR are bidirectional but half-duplex, so only one DMA channel is required at a
time. The data rate for the USB is 12Mbit/sec, which translates to 1.5Mbyte/sec. The data rate
for the FIR is a maximum of 4Mbit/sec, which translates to 0.5Mbyte/sec. The sound output
data rate is 88.2KB/sec. To ensure reasonable usage of SDRAM, APB and ASB bandwidth, the
transfer sizes to these device are:
USB
Quad-word
FIR
Word
Sound
Word
The SDRAM controller will do a complete quad-word access for every SDRAM access. With
the transfer sizes above, the approximate SDRAM bandwidth taken by the devices is:
USB
3%
FIR
4%
Sound
0.75%
The maximum total of SDRAM bandwidth taken by all three devices running concurrently is
7.75%.
DMA accesses to FIR and Sound blocks are fully AMBA compliant, meaning that a word
transfer takes a minimum of two bus cycles to complete. The APB protocol however, for USB
DMA accesses, has been slightly modified to allow burst accesses.
3.3.3 Fly-by
The DMA controller is tightly coupled to the fast APB bridge. In order for the DMA Controller
to start a transfer, it must first receive a DMA data request from one of the peripherals; it will
then request mastership of the ASB.
Once granted, the DMA Controller will retain mastership of the ASB until the requested DMA
transaction is completed, which ensures correct data in the DMA peripherals (that is data in the
DMA peripherals cannot be modified by the ARM processor while a DMA transfer is in
progress).
The DMA transfer request is monitored by the Fast APB bridge, who will perform the
correspondent APB transfer by inverting the read/write line with respect to the ASB, to generate
a PWRITE signal on the APB. The DMA transfer is acknowledged on the APB by asserting a
PSELDMA signal for the given peripheral. The data is timed by PSTB as on a normal APB
transfer. The APB address PA is not used for DMA transfers.
GMS30C7201 Data Sheet
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