GMS30C7201 Datasheet, PDF (319/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Debug and Test Interface
14.3.5 Test Data Registers
Figure 14-2: Boundary Scan Block Diagram illustrates the structure of the boundary scan
logic
BSINENCELL
BSINCELL
BSOUTNENCELL
GMS30C7201
Core Logic
Device ID Register
Bypass Register
Instruction Decoder
BSINCELL
I/O
BSOUTCELL ^Cell
BSOUTCELL
TDO
TDI
Instruction Register
TMS
TCK
nTRST
TAP
Controller
nTDOEN
Figure 14-2: Boundary Scan Block Diagram
Bypass Register
Purpose: This is a single bit register which can be selected as the path between TDI and TDO
to allow the device to be bypassed during boundary-scan testing.
Length: 1 bit
Operating Mode: When the BYPASS instruction is the current instruction in the instruction
register, serial data is transferred from TDI to TDO in the SHIFT-DR state with a delay of one
TCK cycle.
GMS30C7201 Data Sheet
14-9