GMS30C7201 Datasheet, PDF (67/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
ResetStatus register WRITE bits
0
1
2
3
4
5
6
7
8
[12:9]
13
Register bit meaning
Writing a ‘1’ to this bit causes the nPOR event flag
to be cleared.
Writing a ‘0’ has no effect.
Writing a ‘1’ to this bit causes the PLL1 Unlock
event flag to be cleared. Writing a ‘0’ has no effect.
Writing a ‘1’ to this bit causes the PLL2 Unlock
event flag to be cleared. Writing a ‘0’ has no effect.
Writing a ‘1’ to this bit causes the PLL3 Unlock
event flag to be cleared. Writing a ‘0’ has no effect.
OnEvt Interrupt Clear. Writing a ‘1’ to this bit
clears a pending interrupt bit.
RI Interrupt Clear. Writing a ‘1’ to this bit clears a
pending interrupt bit.
RTC Interrupt Clear. Writing a ‘1’ to this bit clears
a pending interrupt bit.
Power Fail Interrupt Clear. Writing a ‘1’ to this bit
clears a pending interrupt bit.
Warm Reset Clear. Writing a ‘1’ to this bit clears
the event bit.
PMU Interrupts Enable. ‘1’ enables interrupts to the
CPU, ‘0’masks such activity. Should the enable bit
be set to one when one of the debounced event
signals is set, then an interrupt WILL be generated
(ie the interrupt is level sensitive, not edge
sensitive).
Warm RESET. Writing a ‘1’ causes nRESET to be
asserted. Writing ‘0’ has no effect.
Table 7-7: Status register WRITE bits
ClkCtl register
This register is used to control the frequency of PLL3, the system clock PLL and PLL1, the
VGA clock. Six bits are defined which control the frequency of FCLK, and a further bit is used
to control the frequency of PLL1, the VGA clock.
The Default (Power on Reset) value for this register is 0x1b.
ClkCtl[5:0]: PLL3Freq
Function
0x1B
49.7664 MHz
0x1C
51.6096 MHz
0x1D
53.4528 MHz
0x1E
55.2960 MHz
0x1F
57.1392 MHz
0x20
58.9824 MHz
0x21
60.8256 MHz
0x22
62.6688 MHz
0x23
64.5120 MHz
Table 7-8: ClkCtl Register
GMS30C7201 Data Sheet
7-11