GMS30C7201 Datasheet, PDF (180/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.5 Transmitting Data
This section deals with the initialization and transmit processes.
12.5.1 Initialization
The principal transfer of data from memory to the active IrDA encoder in MIr and FIr modes is
by DMA. DMA transfers data in 4-byte words into the transmit FIFO when requested by the Ir
block. As data frames are not necessarily a multiple of four bytes in length, there is a mechanism
built into the Ir peripheral for handling any bytes left over at the end of the data frame. This uses
a register called IrDataTail. Before starting Ir transfer, pushing the first two words of data into
the transmit FIFO will reduce system overheads.The Ir peripheral can be configured to provide
an additional level of error checking using the TUS bit in the IrCon register. This monitors the
outgoing data flow and transmits an abort signal to the far end receiver if the transmit FIFO
becomes empty before the end of the frame is reached.
12.5.2 The transmit process
This section describes the transmission process in detail.
Check that the previous transmission is complete
Ensure that the Ir block is not currently receiving or transmitting data by reading the RSY (if
half-duplex communications are in operation) and TBY bits in IrMISR1 or IrFISR1 (depending
on whether MIr or FIr mode is in operation). If either are set, the start of transmission is
postponed.
Select Transmit Underrun Action
Set the TUS bit within the IrCon register to ensure that if the Ir encoder is starved of data it will
signal an abort condition to the far-end receiver.
Pre-loading the Transmit FIFO
Copy the first two full words of data into the transmit FIFO by writing them into the IrData
register.The Ir encode block can hold up to 11 bytes of data (two words in the FIFO plus up to
three bytes in the IrDataTail register). If this is sufficient to hold the complete data packet to be
transmitted, there will be no DMA activity and the IrCon TUS bit should be cleared. This will
cause the Ir encoder to send the CRC and end frame flag correctly.
Setting the DMA Buffer Address, Transfer Length and Mode
DMA channel 1 is used to transfer data to and from the Ir block. The register details can be
found in 12.2.5 DMAC1 Registers on page 12-8.
1 Store the word-aligned address of the source data (not including the data already pre-
loaded into the transmit FIFO) in DMAADR1.
2 Store the Transfer Length (number of words to be transferred by DMA to the Ir FIFO)
in DMATNR1.
3 Clear DMACCR1.MODSEL (selects transfer from memory to IO).
4 Set DMACCR1.mask. This enables end of transfer interrupt.
5 Set DMACCR1.DMEN1. This enables DMA transfer.
6 Ensure that the master enable bit in the DMAC Operation Register is set.
Sending packets which are not a multiple of 4 bytes in length
The FIFO is 32 bits wide. Loading the FIFO with less than 32 bits would cause extraneous zero-
bits to be transmitted. The IrDataTail register is a mechanism used to pre-load the last 1, 2 or 3
bytes of a frame. When the DMA transfer is complete and the transmit FIFO is empty, any bytes
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GMS30C7201 Data Sheet