GMS30C7201 Datasheet, PDF (131/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.2 Video operation
A block diagram of the video system is shown in Figure 11-1: Video System Block Diagram.
The video system has two separate data paths. One data path is for STN LCD and for TFT LCDs,
and the other data path is for the VGA controller. If the frame rate and display resolution are the
same for the LCD and VGA, and if the images are the same, it is possible to share the DMA data
between the two data paths, by writing DMA data into both the input FIFOs. Sharing DMA data
between the data paths has some restrictions in the programming of the VGA and LCD timing
information. This is explained in 11.2.6 Sharing VGA and LCD data on page 11-6.
DMA
data in
VGA DMA
request
VGA
address
Fast APB
interface
LCD DMA
request
LCD
address
FIFO
32x32
FIFO
32x32
VGA
DMA
control
Register
& palette
APB I/F
LCD
DMA
control
LCD/TFT data path
Palette
256x12
Gray-
scale
VGA data path
Palette
256x24
Video
DACs
Format
FIFO
3x8
To LCD
panel
To VGA
monitor
TFT
VGA
Timing
Generator
LCD
Timing
Generator
VGA
control
signals
LCD
control
signals
Figure 11-1: Video System Block Diagram
11.2.1 VGA data path
The VGA data path is the simpler of the two data paths. Data is received from the video ASB
bus into a 32 deep by 32-bit wide asynchronous FIFO. The FIFO data is then extracted into a
holding latch, and multiplexed down to a pixel at a time. This logical pixel data is then passed
to the palette RAM. The palette RAM is composed of three 256 x 8-bit RAMs. There is a RAM
array for each of the R, G and B color components of a pixel. The physical pixel data from the
palette RAM is then passed to the three video DACs.
GMS30C7201 Data Sheet
11-3