GMS30C7201 Datasheet, PDF (82/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
8.5 Power-up Initialization of the SDRAMs
The SDRAMs are initialized by applying power, waiting a prescribed amount of settling time
(typically 100µs), performing some auto-refresh cycles (minimum 2) and then writing to the
SDRAM mode register. The exact sequence is SDRAM device-dependent.
The settling time is referenced from when the SDRAM CLK starts. The processor should wait
for the settling time before enabling the SDRAM controller refreshes, by setting the R bit in the
SDRAM control register. The SDRAM controller automatically provides an auto refresh cycle
for every refresh period programmed into the Refresh Timer when the R bit is set. The processor
must wait for sufficient time to allow the manufacturer’s specified number of auto-refresh
cycles before writing to the SDRAM’s mode register.
The SDRAM’s mode register is written to via its address pins (A[13:0]). Hence, when the
processor wishes to write to the mode register, it should read from the binary address (AMBA
address bits [22:9]), which gives the binary pattern on A[13:0] which is to be written. The mode
register of each of the SDRAMs may be written to by reading from a 64Mbyte address space
from the SDRAM mode register base address. The correspondence between the AMBA address
bits and the SDRAM address lines (A[13:0]) is given in the Row address mapping of Table 8-8:
SDRAM row/column address map on page 8-11. Bits [25:24] of the AMBA address bus select
the device to be initialized.
The SDRAM must be initialized to have the same CAS latency as is programmed into C_[1:0] bits
of the SDRAM control register, and always to have a burst length of 8.
8-10
GMS30C7201 Data Sheet