GMS30C7201 Datasheet, PDF (208/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
The DEV provides the interface between the SIE and the device’s endpoint FIFOs, ROM storing
the device descriptor. The DEV handles the USB protocol, interpreting the incoming tokens and
packets and collecting and sending the outgoing data packets and handshakes.The endpoints
FIFO(RX,TX) give the information of their status (full/empty) to the AMBA interface to
generate DMA request signal and AMBA I/F enable the CPU to access the FIFO’s status
register and the device descriptor stored in ROM. The AMBA interface generates a FIFO read/
write strobe without FIFO’s errors, based on APB signal timing. Automatically it requests the
DMA data handling when RX FIFO is full. In case of data transmitting through TX FIFO (when
USB generates an OUT token, AMBA I/F generates Interrupt to CPU), the user should program
the DMAC to transmitting channel, set the transmitting enable bit in the control register. If the
error of FIFO (Rx: overrun, TX: underrun) occurs, the AMBA I/F cannot generate FIFO read/
write signals and DMA service request signals.
12.10.3Theory of Operation
The LGS USB Core enables a designer to connect virtually any device requiring incoming or
outgoing PC data to the Universal Serial Bus. As illustrated in Figure 12-16: USBD Block
Diagram on page 12-53, the USB core comprises two parts, the SIE and DEV. The SIE connects
to the Universal Serial Bus via a bus transceiver. The interface between the SIE and the DEV is
a byte-oriented interface that exchanges various types of data packets between two blocks.
Serial Interface Engine
The SIE converts the bit-serial, NRZI encoded and bit-stuffed data stream of the USB into a byte
and packet oriented data stream required by the DEV. As shown in Figure 12-17: LGS Serial
Interface Engine, it comprises seven blocks: Digital Phase Lock Loop, Input NRZI decode and
bit-unstuff, Packet Decoder, Packet Encoder, Output bit stuff and NRZI encode, Counters, and
the CRC Generation & Checking block. Each of the blocks is described in the following
sections.
USB
Digital Phase
Lock Loop
NRZI
decode,
bit unstuff
Output
Bit stuff
NRZI
Encoder
Counter
CRC
generation
checking
Packet
Decoder
Device
Interface
Packet
Encoder
Figure 12-17: LGS Serial Interface Engine
12-54
GMS30C7201 Data Sheet