GMS30C7201 Datasheet, PDF (124/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PCMCIA Interface
A total of 256 Mbytes address range is allocated for each PCMCIA Card. (So, there is no need
for an address window as an ISA based PCMCIA card controller is used to access a total 64
Mbyte with very small system address range.) For the fast access support of Mixed I/O and
Memory Card, each region has 64M byte address range.
Address Range
Function Area
0 - 64 Mbyte
Attribute Memory Area
64 - 128 Mbyte
Common Memory Area
64 - 192 Mbyte
I/O Area
192 - 256 Mbyte
Reserved for future use
Table 10-33: Address ranges and function areas
Note
Also, the IOIS16 signal is not used.
External Buffer Requirement:
The external buffer must operate in both 3.3v and 5.0v to support low power cards. CaDRV and
CbDRV control the External buffer to pass the correct signals to the socket. LCX16244 is the
5V tolerant Buffer which has the enable pin. The data buffer must be bidirectional. This
bidirectional port can be easily controlled with an additional control pin. LCX16245 is the 5V
tolerant buffer which has an enable pin and a direction control pin. The PCMCIAOutLEn can
be used for direction control pin of the LCX16245.
Controller Pad Requirement:
Pads must tolerate 5v input from 5v PCMCIA Card.
10.3.2 Interrupt handling
Interrupt handling is the most important role in the PCMCIA Host Bus Controller. Interrupts
are generated from two different sources, the Card Status change interrupt and a Card-generated
interrupt which requires host’s attention, e.g, data transmission buffer is full, so, it’s requires
some read operation from the host. Today, PCMCIA Cards can generate level mode or pulse
mode interrupts. A different mechanism is required for Card status change interrupt handling.
This interrupt source is monitored and change status is saved in relevant registers, the Interface
Status Register and Card Status Change Register. Card Status Change includes the insertion or
removal of the card, battery warning or dead, and so on. Only Level mode interrupt is used in
this type of interrupt source. Each interrupt can be masked by setting the corresponding bit of
the Card Status Interrupt Configuration Register. The host can know the exact interrupt source
by reading the Interface Status Register and Card Status Change Register.
10.3.3 Enhanced power management
Three power down operations are mode supported for enhanced power management. Most
power is saved by disabling the clock to inactive blocks. Power down is entered under software
control.Table 10-34: Power Down Modes provides a summary.
Mode
Partial Power Down
Full Power Down
Summary
Interrupts still operate (to monitor card changes).
All internal control logic disabled.
10-24
GMS30C7201 Data Sheet