GMS30C7201 Datasheet, PDF (32/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Architecture Overview
3.1 Internal bus structure
Figure 3-1: GMS30C7201 shows a block diagram of GMS30C7201. GMS30C7201 consists of
the ARM720T processor core, a Piccolo SP7 DSP coprocessor and a set of peripherals.
32kHz
3.68MHz
STATIC
Memory
I/F and
PC-Card
JTAG
ARM720T
OSC
( RTC)
Piccolo
OSC
PLL
PLL
PLL
60MHz
(CPU)
/2
31.5-40MHz 48MHz
30MHz ^{(VIDEO) (IrDA&USB)}
(BUS)
PMU
ASB 30MHz
SDRAM Controller
DMA
Adrs Data
LCD
Controller
(incl DMAC)
VGA
Cont.
(+DMAC)
Fast
APB
Bridge
DMAC
(peripherals)
Slow
APB
Bridge
3.6864MHz
Slow APB
RTC
INTC
TIMER
Sound
USB
MIR/FIR
UART
SIR
UART
KEYBD
Controller
GPIO
ADC
CODEC
I/F (for
softmodem)
SPI
Figure 3-1: GMS30C7201
3.1.1
GMS30C7201 bus structure
The GMS30C7201 internal bus organization is based upon the AMBA standard, but with some
minor modifications to the peripheral buses (the APBs). There are three main buses in the
GMS30C7201:
1 the main system bus (the ASB) to which the CPU and memory controllers are
connected
2 the fast APB to which high-bandwidth peripherals are connected
3 the slow APB (to which timers, the UART and other low-bandwidth peripherals are
connected)
There is also a separate video DMA bus.
3-2
GMS30C7201 Data Sheet