GMS30C7201 Datasheet, PDF (166/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Channel Control Register 0(CCR0)
This register is channel control register of the interface controller for sound peripheral device.
Bit 0 (DMEN: Enables channel operation)
DMEN
0
1
Description
Disables channel operation (initial value)
Enables channel operation
Bit 1 (MASK0: The mask bit of transfer end interrupt for buffer 0)
Table 12-11: Bit 0
MASK0
0
1
Description
Interrupt request is not generated even if data transfer ends by the
specified count (initial value)
Interrupt request is generated if data transfer ends by the specified
count
Table 12-12: Bit 1
Bit 2 (MASK1: The mask bit of transfer end interrupt for buffer 1)
MASK 1
0
1
Description
Interrupt request is not generated even if data transfer ends by the
specified count (initial value)
Interrupt request is generated if data transfer ends by the specified
count
Table 12-13: Bit 2 Mask 1
Channel Control Register 1(CCR1)
This register is channel control register of Infrared Communication Port(ICP) controller.
Bit 0 (DMEN: Enables channel 1 operation)
DMEN
0
1
Description
Disables channel 1 operation (initial value)
Enables channel 1 operation
Table 12-14: Bit 0
12-12
GMS30C7201 Data Sheet