GMS30C7201 Datasheet, PDF (232/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.2.3 Signal description
The 16C550 UART module is connected to the internal APB bus.
Name
PCLK
Type
In
BnRES
In
PA[5:2]
In
PD[7:0]
InOut
PSTB
In
PWRITE
In
PSEL
In
INTUART Out
SIN
In
Source/
Destination
APB Bridge
APB Bridge
APB Bridge
APB Bridge
APB Bridge
APB Bridge
INTC
External
Description
UART Clock input
This connects the main timing reference to the UART.
3.6864Mhz is input clock frequency recommended.
Reset signal generated from the APB Bridge (Master Reset)
When this input is LOW, it clears all the registers (except the
Receiver Buffer, Transmitter Holding and Divisor Latches) and
the control logic of the UART. The states of various output signals
(SOUT, INTUART, NRTS, NDTR) are affected by an active
BnRES input.
Register select. Address signals connected to these three inputs
select a UART register for the CPU to read from or write to during
data transfer. A table of registers and their addresses is shown
below (Table 13-6: Summary of registers on page 13-10).
Data Bus. This bus comprises eight TRI-STATE input/output
lines. The bus provides bi-directional communications between the
UART and the CPU, Data, control words and status information
are transferred via the PD[7:0] data bus.
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of
BCLK (ASB System Clock).
When HIGH, this signal indicates a write to a peripheral. When
LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes HIGH and remains valid after
PSTB goes LOW.
When HIGH, this signal indicates that this module has been
selected by the APB bridge. This selection is a decode of the
system address bus (ASB).
Interrupt. This pin goes HIGH whenever any one of the following
interrupt types has an active HIGH condition and is enabled via
IER:
Receiver Error Flag
Received Data Available:timeout(FIFO Mode only)
Transmitter Holding Register Empty
MODEM Status
The INTUART signal is reset LOW upon the appropriate interrupt
service or a Master Reset operation.
Serial Input. Serial data input from the communications link
(peripheral device, MODEM or data set).
Table 13-2: Signal descriptions
13-4
GMS30C7201 Data Sheet