GMS30C7201 Datasheet, PDF (286/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
RFIFO
(9x32)
RXDR
RXSR
Rx Block
CODEC Interface
TFIFO
(9x32)
TXDR
TXSR
Tx Block
CR
SR
Control
Block
Figure 13-8: AFE Interface block diagram
Transmit and receive modes are enabled by asserting TREN bit in the control register. When
asserted, the FIFO is enabled. Additionally, if the TREN bit is cleared, the SDO output is
disabled. Asserting the enable bit causes the interrupt generation logic to become active,
otherwise it is disabled.
Data is loaded into the transmit FIFO by writing to the TXDR register. At the beginning of a
transmit cycle, this data is loaded into a shift register where it is shifted out serially to SDO,
MSB first, according to the CODEC protocol mode (See Figure 13-9: CODEC protocol
diagram on page 13-59).
Data is received by taking data in serially through SDI, again MSB first, shifting it through the
shift register and loading the complete half-word into the receive FIFO when a half-word has
been received.
The Status register is provided to indicate the status of the FIFOs, whether an interrupt occurred,
and whether an error occurred.
13-58
GMS30C7201 Data Sheet