GMS30C7201 Datasheet, PDF (174/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Receive Enable (RXE)
The receive enable (RXE) bit is used to enable or disable MIr/FIr receive operation. When
RXE=0, the receive logic is disabled and its clocks are turned off to conserve power. When
RXE=1, the receiver logic is enabled for IrDA reception. It is required that the user first program
all other control bits before setting RXE. If the RXE bit is cleared to zero while the Ir interface
is actively receiving data, reception is stopped immediately, all data within the receive buffer
and serial input shifter is cleared. Clearing RXE to zero ensures the selected Ir receiver is
disabled. Note that RXE is ignored by the SIr (which is always enabled whenever selected by
the IrEnable register).
Also note that even though the IrDA standard only permits half-duplex operation, the FIr does
not restrict the user from transmitting and receiving data at the same time; both are fully
independent units. This function is particularly useful when using the FIr in loop back mode.
Receive buffer Interrupt Mask (RIM)
The receive buffer interrupt mask (RIM) bit is used to mask or enable the receive buffer service
request interrupt. When RIM=0, the interrupt is masked, and the state of the receive buffer
service request (RFS) bit within MIr/FIr status register 0 is ignored by the interrupt controller.
When RIM=1, the interrupt is enabled, and whenever RFS is set (one) an interrupt request is
made to the interrupt controller. Note that programming RIM=0 does not affect the current state
of RFS or the receive buffer logic’s ability to set and clear RFS, it only blocks the generation of
the interrupt request.
Also note that RIM does not affect generation of the receive buffer DMA request which is
asserted whenever both RFS is set and the receiver buffer error/end flag (EIF) is clear.
Transmit buffer Interrupt Mask (TIM)
The transmit buffer interrupt mask (TIM) bit is used to mask or enable the transmit buffer
service request interrupt. When TIM=0, the interrupt is masked and the state of the transmit
buffer service request (TFS) bit within MIr/FIr status register 0 is ignored by the interrupt
controller. When TIM=1, the interrupt is enabled, and whenever TFS is set (one) an interrupt
request is made to the interrupt controller. Note that programming TIM=0 does not affect the
current state of TFS or the transmit buffer logic’s ability to set and clear TFS, it only blocks the
generation of the interrupt request.
TIM does not affect generation of the transmit buffer DMA request which is asserted whenever
TFS is set.
Address Match Enable (AME)
The address match enable (AME) bit is used to enable or disable the receive logic from
comparing the address programmed in the address match value (AMV) bit-field, to the address
of all incoming frames. When AME is set (equals one), data is stored in the receive buffer only
for those frames which have addresses that match AMV, and for any frame which contains the
broadcast address (0hFF). For frames in which the address does not match, the data and CRC
are ignored, and the receiver resumes hunting for another data packet. When AME is clear
(zero), address values are not compared and the data in every frame is stored in the receive
buffer.
Figure 12-3: Location of bits within Ir Control Register shows the location of the bits within
the Ir Control Register. All bits are cleared (set to zero) following a reset of the ARM 7201. Note
that the currently selected Ir interface (MIr or FIr) must be disabled by clearing the enable bits
in this register (RXE=TXE=0) before selecting a different interface using the IrEnable register.
The other bits in this register may be written while the interface is enabled to allow various
modes to be changed during operation.
12-20
GMS30C7201 Data Sheet