GMS30C7201 Datasheet, PDF (238/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.2.5 Registers description
There are two UARTs implemented in the design, the base addresses are U1Base and U2Base.
UART Enable register is explained in page 13-20(Test Regsters of Uart).
In Table 13-5: UART register address map, x can be either 1 or 2.
Address
UxBase + 0x00
UxBase + 0x00
UxBase + 0x04
UxBase + 0x08
UxBase + 0x08
UxBase + 0x0C
UxBase + 0x10
UxBase + 0x14
UxBase + 0x18
UxBase + 0x1C
UxBase + 0x00
UxBase + 0x04
Name
Description
Receiver_Buffer
# 8-bit R/O set DLAB=0
Transmitter_Holding
# 8-bit W/O set DLAB=0
Interrupt_Enable
# 8-bit R/W
Interrupt_Identification
# 8-bit R/O
FIFO_Control
# 8-bit W/O
Line_Control
# 8-bit R/W
MODEM_Control
# 8-bit R/W
Line_Status
# 8-bit R/W
MODEM_Status
# 8-bit R/W
Scratch
# 8-bit R/W
Divisor_Latch_LS
# 8-bit R/W set DLAB=1
Divisor_Latch_MS
# 8-bit R/W set DLAB=1
Table 13-5: UART register address map
Table 13-6: Summary of registers gives details of the UART registers.
Register Address
0 DLAB=0 0 DLAB=0 1 DLAB=0 1
2
3
4
5
6
7
0 DLAB=1 1 DLAB=1
Bit Receiver
No. Buffer
Register
(R/O)
Transmitter
Holding
Register
(W/O)
Interrupt
Enable
Register
Interrupt
Ident
Register
(R/O)
FIFO
Control
Register
(W/O)
Line
Control
Register
Modem
Control
Register
Line Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LS)
Divisor
Latch
(MS)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
0 Data Bit 0 Data Bit 0 Enable
(Note 1)
received
data
available
interrupt
0 if
interrupt
pending
FIFO
enable
Word
length
select
Bit 0
Data
Terminal
Ready
(DTR)
Data Ready
(DR)
Delta Clear Bit
to Send
(DCTS)
0
Bit
0
Bit
1 Data Bit 1 Data Bit 1 Enable
Interrupt RCVR
Word
transmitter ID Bit 0 FIFO reset length
holding
select
register
Bit 1
empty
interrupt
Request to
Send
(RTS)
Overrun
Error
(OE)
Delta Data
Set Ready
(DDSR)
Bit 1
Bit 1
Bit 9
Table 13-6: Summary of registers
13-10
GMS30C7201 Data Sheet