GMS30C7201 Datasheet, PDF (222/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.11.1Hardware interface and signal description
The SOC module is connected to the internal APB bus.
Name
PCLK
BnRES
PA[4:2]
PD[31:0]
PSTB
PWRITE
PSEL
PSELDMA
DRQ
INT
SD[7:0]
IOSTOP
DLEFT
DRIGHT
Type
In
In
In
InOut
In
In
In
In
Out
Out
Out
Out
Out
Out
Source/Destination
Clock controller
APB Bridge
APB Bridge
APB Peripherals,
BD bus
APB Bridge
APB Bridge
APB Bridge
APB Bridge
DMA
Interrupt Controller
DAC
DAC
DAC
DAC
Description
UART clock (3.6864MHz).
Reset signal generated from the APB Bridge.
This is the peripheral address bus, which is used by an individual peripheral for
decoding register accesses to that peripheral.
The addresses become valid before PSTB goes HIGH, and remain valid after
PSTB goes LOW.
This is the bidirectional peripheral data bus. The data bus is driven by this block
during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus. The falling
edge of PSTB is coincident with the falling edge of BCLK.
When HIGH, this signal indicates a write to a peripheral. When LOW, it indicates
a read from a peripheral.
This signal has the same timing as the peripheral address bus. It becomes valid
before PSTB goes HIGH, and remains valid after PSTB goes LOW.
When HIGH, this signal indicates that this module has been selected by the APB
bridge. This selection is a decode of the system address bus (ASB).
For more details, see AMBA Peripheral Bus Controller (ARM DDI0044).
Active HIGH signal provided by the APB Bridge to indicate SoundC DMA
access.
When SD transfers upper 16-bit, this signal requests more sound data for the DAC
with active HIGH until writing the data at SDADR.
When SD transfer upper 16-bit, this signal requests more sound data for the DAC
with active HIGH until writing the data at SDADR.
DAC data bus. During SCLK HIGH, it is upper 8-bit of DataBuf, and during
LOW, the lower 8-bit of DataBuf.
When HIGH, analog circuits in DAC go to rail-to-rail to save power dissipation.
If inactive LOW, the analog circuit in the DAC operates in normal mode.
When HIGH, this signal indicates that converted left data out is stable in DAC.
Left/right signal is non-overlapping signal.
When HIGH, this signal indicates that converted right data out is stable in DAC.
Table 12-43: APB signal descriptions
12.11.2Sound control unit operation
The SOC is an interface block used to send data to the external speaker through the internal 8-
bit DA converter. It can process 44.1/22.05/11.025/8KHz sampled 8-bit mono or 16-bit stereo
sound data.
12-68
GMS30C7201 Data Sheet