GMS30C7201 Datasheet, PDF (176/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.3.5 Ir Address Match Value Register
The Ir Address Match Value Register (IrAmv) contains the 8-bit address match value field
which is used by the MIr and FIr to selectively filter out unwanted received frames.
Address Match Value (AMV)
The 8-bit address match value (AMV) field is programmed with an address value which is used
to selectively store only the data within receive frames which have the same address value. The
address match enable (AME) bit in IrCon must be set to enable this function. For incoming
frames which have the same address value as the AMV field, the frame’s address, control and
data is stored in the receive buffer. For those that do not, the remainder of the frame is ignored,
and the receive logic searches for the beginning of the next frame in the received data stream.
A broadcast address exists which is always matched by the address match logic regardless of
the value programmed in AMV. When address matching is enabled, any time a frame is received
with an address containing all ones (FFh), the value programmed in AMV is ignored and the
frame data is automatically stored in the receive buffer.
The address value is contained within the first byte of data in a frame following the flag. AMV
can be written at any time, and is used for comparison for the next frame which occurs following
its update.
Figure 12-4: Address match value field in the IrAmv Register shows the address match value
field within Ir Address Match Value Register. The reset state of AMV is unknown and must be
initialized before enabling the Ir interface. Note that IrAmv may be written while an Ir interface
is enabled to allow the address match value to be changed during active receive operation.
Address: 0h80011008
Bit
765
AMV
Reset ? ? ?
IrAmv
43
??
Read/Write
210
???
Figure 12-4: Address match value field in the IrAmv Register
Bit
Name
7–0 AMV
Description
Address Match Value
8-bit value used by receiver logic to compare to address of incoming frames. If address
matches store frame address, control and data in receive buffer; if address does not match,
ignore frame and search for preamble.
Note: an address of 0hFF (all 1) in the incoming frame automatically generates a match
(AMV is ignored).
Table 12-26: IrAmv Register
12.3.6 Ir Data Register
The Ir data register (IrData) is a 32-bit register corresponding to the transmit and receive buffers
used by the MIr and FIr interfaces.
12-22
GMS30C7201 Data Sheet