GMS30C7201 Datasheet, PDF (143/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.7 VGA Timing 2 Register
VGA Timing 2 Register (VgaTiming2) controls various functions associated with the timing
and control of the VGA controller.
11.7.1 Invert Vsync (IVS)
The Invert VSync (IVS) bit is used to invert the polarity of the VSync signal. When IVS=1,
VSync is active HIGH. When IVS=0, VSync is active LOW.
11.7.2 Invert Hsync (IHS)
The Invert HSync (IHS) bit is used to invert the polarity of the HSync signal. When IVS=1,
HSync is active HIGH. When IVS=0, HSync is active LOW.
11.7.3 Composite VSync (CVS)
When this bit is set, the VSync signal outputs a composite sync comprised of HSync XNOR
VSync. If the IVS bit is set, it will invert this to produce the XOR of the syncs.
11.7.4 Composite HSync (CHS)
When this bit is set, the HSync pin outputs the logical AND of VSync and HSync. If IHS is set
it will output the NAND of the syncs.
Bit
0-10
11
12
13
14
31-15
Name
-
IVS
IHS
CVS
CHS
-
Description
Reserved
Invert VSync
0 - VSync is a negative edge sync.
1 - VSync is a positive edge sync.
Invert Hsync
0 - HSync is a negative edge sync.
1 - HSync is a positive edge sync.
Composite VSync
Output XNOR of HSync and VSync on VSync pin (XOR if IVS is set)
Composite HSync
Output AND of HSync and VSync on HSync pin (NAND if IHS is set)
Reserved
Table 11-6: VGA TIming 2 Register Functions
GMS30C7201 Data Sheet
11-15