GMS30C7201 Datasheet, PDF (223/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
This unit has a 32-bit register to receive sound data from the CPU through DMA or interrupt
mode. This unit requests the DMA or interrupt controller every 32-bit processing time, which
depends on the sampling frequency. It has two separate signals for DAC which indicate the
direction of data for the stereo sound. Either higher or lower byte of 16-bit stereo sound data can
be played through the left or right speaker by programming the control register. During mono
playback, this unit sends the same data for the left and right channels.
There are two test registers. Both these registers should be cleared during normal operation.
TICCLK port is also assigned for production test only.
12.11.3Sound control unit memory map
The base address of the SOC is variable, and the offset of any particular register from the base
address is fixed.
Address
SOC Base + 0x00
SOC Base + 0x04
SOC Base + 0x08
SOC Base + 0x0C
SOC Base + 0x10
Read Location
Write Location
SCONT[7:0]
SCONT
SDADR[31:0]
SDADR
STOR[17:0]
STOR
STIR[14:0]
TICCLK
TICCLK
Table 12-44: Sound control unit register memory map
12.11.4Sound control unit Register Descriptions
The following registers are provided for the SOC:
• Control Register (SCONT)
• Data Register (SDADR)
• Test Output Register (STOR)
• Test Input Register(STIR)
Refer to Table 12-45: SCONTRL bit description on page 12-70, Table 12-46: SDADR bit
description on page 12-71,
GMS30C7201 Data Sheet
12-69