GMS30C7201 Datasheet, PDF (164/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.2.9 DMAC (Read only) Test Register1
Address
DMA Base + 0x34
R/W Name
R/W TESTR1
Bit
[31:0]
Initialized
to
0
Contents
When in test mode, this register latches the address
of DMAC.
Table 12-8: DMAC Test Register 1
12.2.10DMAC (Read only) Test Register2
Address
DMA Base + 0x38
R/W Name
R/W TESTR2
R
12.2.11DMAC Operation Register
Bit
[0]
[1]
[3:2]
[5:4]
[6]
[8:7]
[31:9]
Initialized
to
0
0
0
0
0
0
0x000000
Contents
BWRITE
DMAC request signal
BSIZE[1:0}
BTRAN[1:0]
TransendINT (the transfer-end interrupt of DMAC)
ChSel[1:0]
Reserved bits
Table 12-9: Test Register 2
Address
DMA Base + 0x3C
R/W Name
R/W DMAOR
R
Bit
[0]
[1]
[2]
[31:3]
Initialized
to
0
0
0
0x0000
Contents
DMAEN (DMAC master enable bit)
PRMD0 (Priority mode bit 0)
PRMD1 (Priority mode bit 1)
Reserved bits
Table 12-10: Test Register 2
12-10
GMS30C7201 Data Sheet