GMS30C7201 Datasheet, PDF (69/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
The first effect that writing a new value to bits [5:0] will have is that PLL3 will go out of lock,
and the Clock control circuit will immediately inhibit FCLK and BCLK, without first verifying
that SDRAM operations have completed.
Debounce counter test register (read)
DbCtr[5:0]
[3:0]
[5:4]
Function
Prescaler bits
Selected debounce counter bits
Table 7-9: DbCtr Register (Read)
Debounce counter test register (write)
DbCtr[2:0]
0x00
0x01
0x03
0x04
Function
Selects debounce counter for nPMWAKEUP
Selects debounce counter for RING event
Selects debounce counter for POWER Adaptor event
Selects debounce counter for Warm Reset
Table 7-10: DbCtr Register Bits[2:0](Write)
DbCtr[3]
1
0
DbCtr[4]
1
0
DbCtr[8]
1
0
Function
forces local test mode
nTEST takes value from input pin
Function
disables Bus Request from the PMU to allow CPU to read state
machine for test purposes during PMU IDLE state.
normal operation
Table 7-11: DbCtr Register Bits[3:4]
Function
Forces FCLK and BLCK to be active in all PMU states (test purposes
only)
Normal operation
Table 7-12: DbCtr Register Bit 8
In order that the debounce counters (which would normally be clocked from 4kHz) may be
independently exercised and observed, the counters may be triggered and observed using the
above registers. These registers are for testing only and are not required in normal use.
GMS30C7201 Data Sheet
7-13