GMS30C7201 Datasheet, PDF (246/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
The contents of the MODEM Status Register are indicated in Table 13-6: Summary of registers
on page 13-10 and described below.
Bit 0:
This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the
NCTS input to the chip has changed state since the last time it was read by
the CPU.
Bit 1:
This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the
NDSR input to the chip has changed state since the last time it was read by
the CPU.
Bit 2:
This bit is the Trailing Edge of Ring Indicator (TERI) detector. Bit 2 indicates
that the NRI input to the chip has changed from a LOW to a HIGH state.
Bit 3:
This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates
that the NDCD input to the chip has changed state since the last time it was
read by the CPU.
Note: Whenever bit 0, 1, 2 or 3 is set to logic 1, a MODEM Status Interrupt
is generated.
Bit 4:
This bit is the complement of the Clear to Send (NCTS) input. If bit 4 (loop)
of the MCR is set to a 1, this bit is equivalent to RTS in the MCR.
Bit 5:
This bit is the complement of the Data Set Ready (NDSR) input. If bit 4 of
the MCR is set to a 1, this bit is equivalent to DTR in the MCR.
Bit 6:
This bit is the complement of the Ring Indicator (NRI) input. If bit 4 of the
MCR is set to a 1, this bit is equivalent to OUT1 in the MCR.
Bit 7:
This bit is the complement of the Data Carrier Detect (NDCD) input. If bit 4
of the MCR is set to a 1, this bit is equivalent to OUT2 in the MCR.
Scratch Register
This 8-bit Read/Write Register does not control the UART in any way. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR 0 = 1, IER 0 = 1) RCVR
interrupts occur as follows:
1 The received data available interrupt will be issued to the CPU when the FIFO has
reached its programmed trigger level. It will be cleared as soon as the FIFO drops
below its programmed trigger level.
2 The IIR receive data available indication also occurs when the FIFO trigger level is
reached, and like the interrupt, it is cleared when the FIFO drops below the trigger
level.
3 The receiver line status interrupt (IIR-06), as before, has higher priority than the
received data available (IIR-04) interrupt.
4 The data ready bit (LSR 0) is set as soon as a character is transferred from the shift
register to the RCVR FIFO. It is reset when the FIFO is empty.
13-18
GMS30C7201 Data Sheet