GMS30C7201 Datasheet, PDF (215/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Clock signal
Signal Name
CCLK
Type
in
Description
CCLK. This pin is driven by an internal 48MHz PLL. The digital phase-lock
loop within SIE uses this signal to capture the USB data, as well as divide it
down to provide a 12MHz clock for the rest of the core and device. This signal
should have a 40%-60% duty cycle, and is positive-edge sensitive.
Table 12-40: Clock Signal 48
12.10.8Internal Registers
Table 12-41: USB register address map summarizes the USB internal registers.
Address
Base address + 0x00
Base address + 0x04
Base address + 0x08
Base address + 0x0C
Base address + 0x10
Base address + 0x14
Base address + 0x18
Base address + 0x1C
Base address + 0x20
Base address + 0x24
Name
CONT0
CONT1
RXDATA
TXDATA
STATUS
TicRXDATA
TicTXDATA
TicSEL
TicREG
TicRESULT
CONTswreset
CONTdrqmask
Description
USB I/F control register 0
USB I/F control register 1
USBD receive data register
USBD transmit data register
USBD status register
USBD receive data register for TIC mode
USBD transmit data register for TIC mode
TIC mode select register
Input TIC register for TIC mode
Output TIC register for TIC mode
Generate software reset to USBD
DMAC request masking register
Table 12-41: USB register address map
CONT0 (USB I/F control register0) (Base address +0x00)
Bit
7
6
5
4
3
2
1
0
RESERVED
TXEN
GMS30C7201 Data Sheet
12-61