GMS30C7201 Datasheet, PDF (36/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Architecture Overview
The APB bridge receives two signals from the DMA controller called CHAN[1:0], which tells
it which DMA channel (peripheral) the DMA access is for. All other information comes from
monitoring the ASB bus signals. For example, the direction of transfer comes from BWRITE
(the sense is inverted to get the APB signal), and when the SDRAM transfer completes, comes
from the bridge monitoring the BWAIT ASB signal.
3.3.4 Timing
This is detailed in Chapter 12, Fast AMBA Peripherals.
3.3.5
Slow APB peripherals
Since the DMA controller is not coupled with the slow APB bridge, it is not possible to use
DMA with devices on the slow APB bus. However, since devices on the slow APB bus are
inherently low performance, this is not a serious restriction. Devices on the slow APB bus must
use the ARM acting under interrupt control to simulate DMA. The highest data rate peripheral
on the slow APB bus is the modem CODEC interface, at a maximum of 48KB/sec. The ARM
FIQ is used to transfer data to the CODEC.
3.3.6 Sound output
In the GMS30C7201, the sound peripheral is located on the fast APB bus, and is supported by
the DMA controller. (Note that this is compatible with some operating systems, which require
DMA-support sound hardware.)
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GMS30C7201 Data Sheet